Top layers of metal for integrated circuits

ABSTRACT

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

This is a continuation application of application Ser. No. 10/948,020,filed on Sep. 23, 2004, now pending

RELATED PATENT APPLICATIONS

This application is related to attorney docket number MSL98-002CCCCIPSer. No. 10/154,662 filed on May 24, 2002, a continuation-in-partapplication of Ser. No. 10/058,259, filed on Jan. 29, 2002, now issuedas U.S. Pat. No. 6,660,728, which is a continuation application of Ser.No. 09/251,183, filed on Feb. 17, 1999, now issued as U.S. Pat. No.6,383,916, which is a continuation-in-part application of Ser. No.09/216,791, filed on Dec. 21, 1998, abandoned, all of which are hereinincorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the manufacturing of high performance, highcurrent, low power, and/or low voltage Integrated Circuit (IC's), andmore specifically to methods of achieving high performance of theIntegrated Circuits by reducing the capacitance and resistance ofinter-connecting wiring on chip.

2. Description of the Related Art

When the geometric dimensions of Integrated Circuits are scaled down,the cost per die is decreased while some aspects of performance areimproved. The metal connections which connect the Integrated Circuit toother circuit or system components become of relative more importanceand have, with the further miniaturization of the IC, an increasinglynegative impact on the circuit performance. The capacitance andresistance of the metal interconnections increase, which degrades thechip performance significantly. Of most concern in this respect is thevoltage drop along the power and ground buses and the RC delay of thecritical signal paths. Attempts to reduce the resistance by using widermetal lines result in higher capacitance of these wires.

To solve this problem, the approach has been taken to develop lowresistance metal (such as copper) for the wires while low-k dielectricmaterials are used in between signal lines. From the aspect of IC metalinterconnection history, sputtered aluminum has been a mainstream ICinterconnection metal material since the 1960's. The aluminum film issputtered to cover the whole wafer, and then the metal is patternedusing photolithography methods and dry and/or wet etching. It istechnically difficult and economically expensive to create thicker than2 μm aluminum metal lines due to the cost and stress concerns of blanketsputtering. About 1995, damascene copper metal became an alternative forIC metal interconnection. In damascene copper, the insulator ispatterned and copper metal lines are formed within the insulatoropenings by blanket electroplating copper and chemical mechanicalpolishing (CMP) to remove the unwanted copper. Electroplating the wholewafer with thick metal creates large stress. Furthermore, the thicknessof damascene copper is usually defined by the insulator thickness,typically chemical vapor deposited (CVD) oxides, which does not offerthe desired thickness due to stress and cost concerns. Again it is alsotechnically difficult and economically expensive to create thicker than2 μm copper lines.

U.S. Pat. No. 5,212,403(Nakanishi) shows a method of forming wiringconnections both inside and outside (in a wiring substrate over thechip) for a logic circuit depending on the length of the wireconnections.

U.S. Pat. No. 5,501,006(Gehman, Jr. et al.) shows a structure with aninsulating layer between the integrated circuit (IC) and the wiringsubstrate. A distribution lead connects the bonding pads of the IC tothe bonding pads of the substrate.

U.S. Pat. No. 5,055,907(Jacobs) discloses an extended integrationsemiconductor structure that allows manufacturers to integrate circuitrybeyond the chip boundaries by forming a thin film multi-layer wiringdecal on the support substrate and over the chip.

U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layerinterconnect structure of alternating polyimide (dielectric) and metallayers over an IC in a TAB structure.

U.S. Pat. No. 5,635,767(Wenzel et al.) teaches a method for reducing RCdelay by a PBGA that separates multiple metal layers.

U.S. Pat. No. 5,686,764(Fulcher) shows a flip chip substrate thatreduces RC delay by separating the power and I/O traces.

Stanley Wolf in Silicon Processing for the VLSI Era, Vol. 2, pp.214-217, Lattice Press, Sunset Beach, Calif. c. 1990, discusses the useof polyimide as an intermetal dielectric in the 1980's. However, manydrawbacks of using polyimide are listed and polyimide has not been usedfor this purpose much in the time period since then.

SUMMARY OF THE INVENTION

It is the primary objective of the present invention to improve theperformance of High Performance Integrated Circuits.

Another objective of the present invention is to reduce resistivevoltage drop of the power supply buses that connect the IC tosurrounding circuitry or circuit components.

Another objective of the present invention is to reduce resistance ofthe power supply buses for high current ICs.

Yet another objective of the present invention is to reduce resistanceof IC metal interconnection for low voltage ICs.

Another objective of the present invention is to reduce resistance andload of IC metal interconnection for low power ICs.

A further objective of the present invention is to reduce the RC delayconstant of the signal paths of high performance IC's.

A still further objective of the present invention is to facilitate theapplication of IC's of reduced size and increased circuit density.

Yet another objective of the present invention is to further facilitateand enhance the application of low resistance conductor metals.

Yet another objective of the present invention is to further facilitateand enhance the application of low capacitance conductor metals.

Yet another objective of the present invention is to allow for increasedI/O pin count for the use of high performance IC's.

Yet another objective of the present invention is to simplify chipassembly by reducing the need for re-distribution of I/O chipconnections.

Yet another objective of the present invention is to facilitate theconnection of high-performance IC's to power/ground buses.

Yet another objective of the present invention is to facilitate theconnection of high-performance IC's to clock distribution networks.

Yet another objective of the present invention is to reduce ICmanufacturing costs by allowing or facilitating the use of lessexpensive process equipment and by accommodating less strict applicationof clean room requirements, as compared to sub-micron manufacturingrequirements.

Yet another objective of the present invention is to be a driving forceand stimulus for future system-on-chip designs since the presentinvention allows ready and cost effective interconnection betweenfunctional circuits that are positioned at relatively large distancesfrom each other on the chip.

Yet another objective of the present design is to form the basis for acomputer based routing tool that automatically routes interconnectionsthat exceed a pre-determined length in accordance with the type ofinterconnection that needs to be established.

The present invention adds one or more thick layers of polymerdielectric and one or more layers of thick, wide metal lines on top ofthe finished device wafer passivation. The thick layer of dielectriccan, for example, be of polyimide or benzocyclobutene (BCB) with athickness of over, for example, 3 micrometers. The thick, wide metallines can, for instance, be of electroplated copper or gold. Theselayers of dielectric and metal lines are of primary benefit for longsignal paths and can also be used for power/ground buses or power/groundplanes, clock distribution networks, critical signal, or re-distributionof I/O pads for flip chip applications. The resistance times capacitance(RC product) of the thick, wide metal lines is substantially smallerthan the RC product of the fine line metallization structure under thepassivation.

Furthermore, a method for forming a post-passivation, top metallizationsystem for high performance integrated circuits is provided. Anintegrated circuit is provided, having devices formed in and on asemiconductor substrate. An overlaying fine line interconnectingmetallization structure with first metal lines is connected to thedevices, and has a passivation layer formed thereover, with firstopenings in the passivation layer to contact pads connected to the firstmetal lines. A top metallization system is formed above the passivationlayer, connected to the interconnecting metallization structure, whereinthe top metallization system has top metal lines, in one or more layers,having a thickness and width substantially greater than the first metallines, and wherein the top metallization system connects portions of theinterconnecting metallization structure to other portions of theinterconnecting metallization structure. Significantly, the RC productof the top metallization system is substantially smaller than the RCproduct of the interconnecting metallization structure under thepassivation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a-1 b show a cross section of the interconnection scheme of thepresent invention.

FIGS. 2 a and 2 b show cross sections of the present invention in a morecomplex circuit configuration.

FIGS. 3 a-3 j shows a method of forming the post-passivation scheme fortransitioning from a fine-line interconnection to the post passivationinterconnection of the invention.

FIGS. 4 a and 4 b show an extension of the IC interconnect scheme byadding power, ground and signal distribution capabilities.

FIG. 5 a shows detail regarding a fan-out function in a flip-chip BGAdevice.

FIG. 5 b shows a schematic view of fan-out connections between top padsof post-passivation metal scheme and lower pads of fine-line metalscheme using the post-passivation interconnection to replace the fan-outfunction of the BGA substrate interconnection as in the example of FIG.5 a.

FIG. 6 a shows detail regarding a pad relocation function in a flip-chipBGA device.

FIG. 6 b shows a schematic view of pad relocation connections betweentop pads of post-passivation metal scheme and lower pads of fine linemetal scheme using the post-passivation interconnection to replace thepad relocation function of the BGA substrate interconnection as in theexample of FIG. 6 a.

FIG. 7 a shows detail regarding the usage of common power, ground andsignal pads in a flip-chip BGA device.

FIG. 7 b shows a schematic view of common power, ground and signal padconnections between top pads of post-passivation metal scheme and lowerpads of fine line metal scheme) using the post-passivationinterconnection to replace the common pad function of the BGA substrateinterconnection as in the example of FIG. 7 a.

FIG. 8 a shows detail regarding pad addition in a flip-chip BGA device.One contact pad on the chip is connected to several contact points onthe BGA substrate.

FIG. 8 b shows a schematic view of pad addition connections between toppads of post-passivation metal scheme and lower pads of fine line metalscheme using the post-passivation interconnection to replace the padaddition function of the BGA substrate interconnection as in the exampleof FIG. 8 a. One contact point on the fine line metal scheme isconnected to several contact points of the post-passivation scheme.

DETAILED DESCRIPTION OF THE INVENTION

The present invention teaches an Integrated Circuit structure where keyre-distribution and interconnection metal layers and dielectric layersare added over a conventional IC. These re-distribution andinterconnection layers allow for wider buses and reduce conventional RCdelay.

FIG. 1 a shows a cross-sectional representation of a general view of theinvention. Devices 2 are formed in and on a semiconductor substrate 1,and metallization is accomplished in one or more layers of ICInterconnection 3, above the device layer. These metal layers arereferred to as fine line metal interconnections. Typically, theintermetal dielectric (IMD) layers comprise silicon-based oxides, suchas chemical vapor deposited (CVD) silicon oxide, CVD TEOS oxide,spin-on-glass (SOG), fluorosilicate glass (FSG), high density plasma CVDoxides, or the composite layer formed by a portion of this group ofmaterials. The IMD layers typically have a thickness of between about1,000 and 10,000 Angstroms. The fine line metal interconnections aretypically formed by sputtering aluminum or an aluminum alloy andpatterning the aluminum to form the fine metal lines. Alternatively, thefine lines may be formed by a copper damascene process. In the copperdamascene process, the copper is protected by an adhesion/barrier layernot only underlying the copper, but also surrounding the copper at thesidewalls of the line through the IMD in order to prevent the migrationof copper ions which could adversely affect the underlying activedevices. These fine lines typically have a thickness of between about1,000 and 10,000 Angstroms. In the fabrication process of the fine linemetal interconnections, a clean room environment of class <=10 istypical. That is, no more than 10 particles larger than 0.5 micrometersare found in any given cubic foot of air. The fine line IC metal isfabricated using 5× steppers or scanners or better and using aphotoresist layer having thickness of less than about 5 micrometers. TheIC interconnection connects the devices to one another to formoperational circuits, and also has in its top layer of metal points ofelectrical contact (such as bond pads), which provide connections fromthe IC interconnection layer to outside of the IC.

A passivation layer 4 covers the IC interconnection scheme, whileproviding openings to the electrical contact points. The most frequentlyused passivation layer in the present state of the art is plasmaenhanced CVD (PECVD) oxide and nitride. In creating layer 4, a layer ofapproximately 0.5 micrometers PECVD oxide is deposited first followed bya layer of greater than approximately 0.3 micrometers and preferably,about 0.7 micrometers nitride. Passivation layer 4 is very importantbecause it protects the device wafer from moisture and foreign ioncontamination. At least a nitride layer of greater than about 0.3micrometers thick must be used in order to adequately prevent mobile ionand/or moisture penetration. The positioning of this layer between thesub-micron process (of the integrated circuit) and the tens-micronprocess (of post-passivation technology 80) is of critical importancesince it allows for a cheaper process that has less stringent clean roomrequirements for the process of creating the interconnectingmetallization structure above passivation 4.

In addition to PECVD oxide and PECVD nitride, passivation layer 4 mayalso be formed of silicon oxynitride, phosphosilicate glass (PSG),borosilicate glass (BSG), borophosphosilicate glass (BPSG), orcombinations thereof.

In a key aspect of the invention, the passivation openings can be assmall as 0.1 micrometers. In another critical aspect of the invention, aselective deposition process is used to form the Post PassivationTechnology segment 80, in which metal lines are formed having asubstantially smaller RC product than that of the metal lines in the ICInterconnection layer. More detail is provided below.

Referring now more specifically to FIG. 1 b, there is shown a crosssection of one implementation of the present invention. A siliconsubstrate 1 has transistors and other devices, typically formed ofpolysilicon and other materials, covered by a dielectric layer 2deposited over the devices and the substrate. Source and draindiffusions 120 are shown within the substrate. Layer 3 indicates thetotality of metal layers and dielectric layers that are typicallycreated on top of the device layer 2. Points of contact 6, such asbonding pads known in the semiconductor art, are in the top surface oflayers 3 and are part of layer 3. These points of contact 6 are pointswithin the IC arrangement that need to be further connected tosurrounding circuitry, that is to power lines or to signal lines. Apassivation layer 4, formed of for example silicon nitride, is depositedon top of layer 3, as is known in the art for protecting underlyinglayers from moisture, contamination, etc.

The key steps of the invention begin with the optional deposition of athick insulating layer 5 of a polymer. Layer 5 is a thick polymerinsulating layer (for example polyimide) that has a thickness in excessof 2 micrometers (after curing). The range of polymer thickness can varyfrom 2 micrometers to 100 micrometers, dependent on electrical designrequirements. The polymer insulating layer 5 is thicker than theintermetal dielectric layers in the interconnecting, fine-line,metallization structure by 2 to 500 times.

For the deposition of layer 5 the polymer can be spin-on coated andcured. After spin-on coating, the polymer will be cured at 380 degreesC. for 4 hours in a vacuum or nitrogen ambient. For thicker polymer, thepolymer film can be multiple coated and cured. Alternatively, thepolymer layer can deposited by screen printing or by laminating a drylayer of polymer.

A polymer such as a polyimide (HD Microsystems, Parlin, N.J.) can beused as the polymer. Another material that can be used to create layer 5is the polymer benzocyclobutene (BCB) (Dow Chemical Company, Midland,Mich.), which has recently gained acceptance to be used instead oftypical polyimide application. Yet other possible materials for layer 5include a silicone elastomer or parylene. The epoxy-based material suchas photoepoxy SU-8 (Sotec Microsystems, Renens, Switzerland) can also beused.

A pattern 7 is exposed and etched through the polymer insulating layer 5and the passivation layer 4 over the contact points 6. First metal layer10 is then selectively deposited to contact points 6 through the polymerand passivation layers, as hereinafter described.

In one important aspect of the current invention, referring now to FIGS.3 a-3 j, and specifically FIG. 3 a, openings 7 in the polymer insulatinglayer 5 may be larger than openings 7′ in the passivation layer 4.Openings 7′ may be formed to as small as 0.1 μm, and may range in sizefrom between about 0.1 and 50 μm. Openings 7 in the polymer insulatinglayer 5 may be greater than or equal to about 2 μm. These smallpassivation vias 7′ are advantageous for the following reasons:

-   -   (1) Small passivation vias only need small underlying metal pads        (or dog bone structures); and these small metal pads will not        block the routing capability of the top layer metal in the IC        fine line interconnection scheme.    -   (2) Since the thickness of the inter-metal-dielectric (IMD) in        the IC fine line interconnection is thin, a small metal pad        provides reduced capacitance.

Electrical contact with the contact points 6 can now be established byfilling the openings 7 (and 71) with a conductor. Simultaneously withfilling of the openings 7, a first interconnect metal layer may beformed, as shown in FIG. 3 a. The process steps are described in FIGS. 3b-3 j. In FIGS. 3 a and 3 b, a photo-sensitive polymer insulating layer5 is deposited over the passivation layer 4 and the passivation opening7′. The deposited polymer is then exposed to create openings 7 aligningwith the passivation opening 7′. In FIG. 3 c, a thick metal layer isformed by first sputtering an adhesion/barrier layer 200. Theadhesion/barrier layer is formed of titanium tungsten (TiW), chromium(Cr), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN),and is deposited to a thickness of between about 0.01 and 3 micrometers.An electroplating seed layer 202 is then deposited by sputtering, theseed layer material being copper (Cu), gold (Au), silver (Ag), palladium(Pd) or nickel (Ni), formed to a thickness of between about 0.05 and 3micrometers. Cu is used as the seed layer when copper is to beelectroplated, Au used as the seed layer for plating gold, Ag used asthe seed layer for plating silver, Pd used as seed layer for platingpalladium, and Ni used as seed layer for plating nickel.

A thick photoresist 203, as depicted in FIG. 3 d, of between about 2 and100 micrometers thickness, is next deposited and patterned over the seedlayer. In a selective deposition process, a thick layer of metal, suchas copper (Cu), gold (Au), silver (Ag), palladium (Pd) or nickel (Ni),is then electroplated to a thickness of between about 2 and 100micrometers, as shown in FIG. 3 e, to form thick, wide metalinterconnections 204 and to fill openings 7 and 71. Thus, a selectivedeposition process forms the post-passivation metal structure. Anadvantage of the selective deposition process of the invention is aminimization of wasted material, especially when precious metal, such asgold, silver, or palladium is used. In the selective deposition process,the metal is electroplated only where it is needed. In contrast, in thestandard metal damascene process used for fine line metallization, metalis electroplated everywhere and then etched or polished away where it isnot needed. Covering the whole wafer with thick metal creates stresswhich causes the process problem. This is a waste of metal, especiallyfor the cases when precious metal is used. The removed metal is oftencontaminated and may not be able to be reused or may be very expensiveto be reused.

Furthermore, in the selective deposition process of the invention, thethickness of selective electroplated metal is defined by the thicknessof photoresist, which can be formed as thick as 100 micrometers. Inother words, it is feasible and cost-effective to form thick metal byselective electroplating. By contrast, it is technically difficult toform thick metal by a damascene copper process. A primary limitation toforming thick copper damascene lines is the thickness of the chemicalvapor deposited (CVD) oxides which define the damascene copperthickness. CVD oxides cannot be thickly deposited due to stressconcerns. It is also very expensive to deposit thick CVD oxides.

Referring now to FIGS. 3 f and 3 g, the photoresist is then stripped,and portions of the seed metal and adhesion metal removed, using thethick metal as an etch mask. During the self-aligned wet etching of theadhesion/barrier layer, an undercut 205 is formed in theadhesion/barrier layer 200, as shown in FIG. 3 g. The undercut isusually between about 0.03 to 2.0 micrometers per side, depending onetching recipe and over-etch time. The structure of the thick, wide,post-passivation metal interconnections is different from the structureof the fine line interconnections. In addition to the undercut 205 inthe adhesion/barrier layer, there is a clear boundary between thesputtered thin gold layer 202 and the electroplated thick gold 204. Thiscan be seen, for example, in a transmission electron microscope (TEM)image. The boundary is due to different grain sizes and/or grainorientation in the two gold layers 202 and 204. For example, in a 1,000Angstroms thick sputtered gold layer 202 under a 4 micrometers thickelectroplated gold layer 204, the grain size of the sputtered gold layer202 is about 1,000 Angstroms, and the grain boundary is perpendicular tothe surface of substrate. The grain size of the electroplated gold 204is greater than 2 micrometers with the grain boundary not perpendicular,and typically, at an angle of about 45 degrees from the substratesurface. In the fine line metal interconnections, there is noundercutting or clear boundary of grain size difference inside thealuminum layer.

Where Cu is used for electroplating, an optional nickel cap layer 206may be used to prevent copper corrosion, as shown in FIG. 3 h.Additionally, the adhesion/barrier layer 200 in the post-passivationmetal structure is formed only under the copper line, as shown in FIG. 3h. In the copper damascene process of the fine line metallization, theadhesion/barrier layer is adjacent to the copper not only at the bottom,but also at the sidewalls of the copper line.

In more detail, the clean room environment of the post-passivation metalprocess can be class 100 or more; that is, containing more than 100particles larger than 0.5 micrometers in any given cubic foot of air.During photolithography in the post-passivation metal process, alignersor 1× steppers are used with a photoresist having a thickness of greaterthan about 5 micrometers. This contrasts with the fine line IC metal,fabricated using 5× steppers or scanners or better in a class 10environment or better and using a photoresist layer having thickness ofless than 5 micrometers. The thick, wide metal lines have a thickness ofbetween about 2 and 100 micrometers and a width of greater than about 2micrometers. Furthermore, the spacing between two adjacent thick, widemetal lines at the same layer is greater than about 2 micrometers.

Subsequent metal layers may be formed in a similar manner to that shownfor the first metal layer in FIGS. 3 a-h. For example, referring to FIG.3 i, another thick intermetal polymer layer 222 is deposited over theinterconnect line 204 as described above and an opening 223 formed forconnection of the next metal layer to the first metal layer. A step 222′exists in the intermetal polymer layer at the edge of the underlyingthick metal. Polymer like polyimide is usually a good planarizationmaterial, especially in filling small metal gaps. However, the degree ofplanarization is not 100%. For post-passivation thick metal, theintermetal polymer layer may require a planarization process. FIG. 3 jshows a polymer layer planarized by the chemical-mechanical polishing(CMP). The step 222′ in FIG. 3 i disappears in FIG. 3 j. CMP can beperformed before or after the intermetal polymer opening is formed.Adhesion and electroplating seed layers are then sputtered, a thickphotoresist deposited and the next thick, wide metal layerelectroplated, in a similar manner to the first metal layer. It will beunderstood that the intermetal polymer layer 222 can be deposited in alike manner over the thick, wide metal line having the nickel cap, asshown in FIG. 3 h. The intermetal polymer can be planarized or not, asshown in FIGS. 3 j and 3 i, respectively.

The thick, wide metal 204 of the post passivation process of theinvention is thicker then the typical fine-line metal layers 3 by aratio of between about 2 and 1000 times. The thick, wide metal layersare formed into interconnecting lines that also are wider than thefine-line metal by a ratio of between about 2 and 1000 times. The thick,wide metal lines have a thickness of between about 2 and 100micrometers, and a width of greater than or equal to 2 μm. Line spacingpreferably is greater than or equal to 2 μm. Thicker, wider metal in thepost-passivation process of the invention reduces the resistance ofthese interconnections.

Resistance of metal interconnections in an integrated circuit isdetermined by the material to be used and metal thickness and width,while capacitance is related to dielectric types, thickness, and metalline width, spacing, and thickness. Metal capacitance includes threecomponents: 1) plate capacitance which is a function of the metal widthto dielectric thickness aspect ratio, 2) coupling capacitance which is afunction of the metal thickness to line spacing aspect ratio, and 3)fringing capacitance which is a function of metal thickness, spacing,and dielectric thickness.

In a first example, to the extreme of the fine line metal capability,fine line metal thickness is about 2 micrometers, fine line metal widthis about 10 micrometers, fine line IMD thickness is about 2 micrometers,and the line spacing is about 10 micrometers. Post-passivation metalthickness is about 5 micrometers, metal width is about 10 micrometers,dielectric thickness is about 5 micrometers, and lines spacing is alsoabout 10 micrometers. The metal thickness difference results in a 2.5times reduction in resistance in the post-passivation metal structureover the fine line metal structure. The dielectric thickness results ina 2.5 times difference in capacitance in the post-passivation metalstructure over the fine line metal structure. Then, the reduction inresistance times capacitance (RC product) is 6.25 times, or about 5times.

In a second example, fine line metal thickness is about 1 micrometers,fine line metal width is about 10 micrometers, fine line IMD thicknessis about 0.5 micrometers, and the line spacing is about 2 micrometers.Post-passivation metal thickness is about 5 micrometers, metal width isabout 10 micrometers, dielectric thickness is about 5 micrometers, andlines spacing is about 10 micrometers. The metal thickness differenceresults in about a 5 times reduction in resistance in thepost-passivation metal structure over the fine line metal structure. Thecapacitance is dominated in this case by plate capacitance with areduction of 10 times difference in capacitance in the post-passivationmetal structure over the fine line metal structure. Then, the reductionin RC product is about 50 times.

In a third example, typical capability fine line metal thickness isabout 0.4 micrometers, fine line metal width is about 0.2 micrometers,fine line IMD thickness is about 0.4 micrometers, and the line spacingis about 0.2 micrometers. Post-passivation metal thickness is about 5micrometers, metal width is about 10 micrometers, dielectric thicknessis about 5 micrometers, and line spacing is about 10 micrometers. Themetal thickness difference results in about a 625 times reduction inresistance in the post-passivation metal structure over the fine linemetal structure. The capacitance is dominated by coupling capacitanceand results in about a 4 times difference in capacitance in thepost-passivation metal structure over the fine line metal structure.Then, the reduction in RC product is about 2,500 times.

In a fourth example, typical capability fine line metal thickness isabout 0.4 micrometers, fine line metal width is about 0.2 micrometers,fine line IMD thickness is about 0.4 micrometers, and the line spacingis about 0.2 micrometers. Post-passivation metal thickness is about 10micrometers, metal width is about 10 micrometers, dielectric thicknessis about 10 micrometers, and line spacing is about 40 micrometers. Themetal thickness difference results in about a 1250 times reduction inresistance in the post-passivation metal structure over the fine linemetal structure. The capacitance is dominated by coupling capacitanceand results in about an 8 times difference in capacitance in thepost-passivation metal structure over the fine line metal structure.Then, the reduction in RC product is about 10,000 times.

Summarizing the above discussion, the RC product of the post-passivationmetal structure can be about 5 to 10,000 times smaller than the RCproduct of the fine line metal structure.

It is difficult to achieve 100 times smaller RC product for the toplayer metal of a fine line metallization system when compared to thebottom layer metal in the fine line metal interconnection process. Forexample, the metal line resistance at the top layer metal can be reducedby designing a wide piece of metal, while the capacitance of that metalline will be increasing accordingly (because the IMD is thin).Essentially, it is hard for fine line IC metals to achieve even 10 timessmaller RC product for its top metal layer versus its bottom metallayer.

In one embodiment of the invention, insulating polymer layer 5 may beomitted, with the thick metal layer formed directly on passivation layer4 and connecting to the underlying metal pads.

Co-pending U.S. patent application Ser. No. 10/154,662, attorney docketnumber MSL98-002CCCCIP filed on May 24, 2002, herein incorporated byreference in its entirety, describes variations of the above-describedprocess for forming the thick metal layers, including damasceneprocesses. The RC product of the thick, wide, metal lines formed bythese other methods is still significantly smaller than the RC productof the fine line metal lines, as detailed above.

Referring now back to FIG. 1 b, the tops of the top metal conductor cannow be used for connection of the IC to its environment, and for furtherintegration into the surrounding electrical circuitry. Metal structures10 and 26 are shown; these metals can be of any design in width andthickness to accommodate specific circuit design requirements. Metalstructure 10 can, for instance, be used as a wirebonding pad, or a padfor a solder bump or a gold bump. Metal structure 26 can be used forpower distribution or as a ground or signal bus.

FIGS. 2 a and 2 b show how the present invention as indicated in FIG. 1b can be further extended to include multiple layers of metal. The lowerlevel build up of this cross section is identical to the build up shownin FIG. 1 b with a silicon wafer 1, the poly silicon layer 2, the metaland dielectric combined layer 3, the passivation layer 4, the insulatingpolymer layer 5 and the first metal 10, formed by selective depositionon top of layer 5. The function of the structure that has been describedin FIG. 1 b can be further extended by depositing another layer ofintermetal polymer 14 on top of the previously deposited insulatingpolymer layer 5 and overlying the first metal 10. Selective depositionis used for second metal 12. This second metal 12 can be connected withfirst metal 10 through opening 13. Depositing second metal 12 on top oflayer 14 can thus further extend this process. Additional alternatinglayers of intermetal polymer and metal lines and/or power or groundplanes may be added above layers 12 and 14, as needed. A top polymerlayer 16 may be formed as shown. Opening 27 may be made in the toppolymer layer 16 for connection to external circuits or for testing.Connections may be made to external circuits through solder bumps, goldbumps, or wirebonds.

Since polymer, for example polyimide, cannot perfectly planarizeunderlying steps, gaps, or dips, there are concerns in the subsequentprocesses. In the post-passivation process, the thick metal creates bigsteps and gaps, and the thick polymer dielectric in addition generatesdeep openings. In FIG. 2 a, openings 5′ in the polymer insulating layer5 results in dips 10′ at the surface of the first post-passivation metallayer 10. In addition to the dips 10′, there is a metal gap 10″ betweentwo pieces of the first metal 10. The dips 10′ and gap 10″ furtherresult in dips 14′ at the surface of the first intermetal polymer layer14, dips 12′ at the surface of the second metal layer 12, and dips 16′at the surface of the top polymer layer 16. In FIG. 2 b, the firstintermetal polymer layer 14 is planarized by chemical-mechanicalpolishing (CMP). Dips 14′ at the surface of the first intermetal polymerlayer 14, dips 12′ at the surface of the second metal layer 12, and dips16′ at the surface of the top polymer layer 16, all shown FIG. 2 a, donot appear in FIG. 2 b using the CMP process.

The insulating polymer layer 5 and intermetal polymer layer 14 that areformed between the thick, post-passivation metal lines are formed to athickness of between about 2 and 30 micrometers, after curing, and arethicker than the intermetal dielectric layers formed in the typicalfine-line metal scheme (layers 3) by a ratio of between about 2 and 500.The thicker, organic polymer used in the post-passivation process of theinvention reduces capacitance between the thick metal lines. Theinorganic materials, such as silicon oxide, used in the fine-linemetallization system 3, cannot be formed to such thicknesses due to atendency to crack at these thicknesses. This reduced capacitance reducesRC product of the post passivation metal system of the invention, asdescribed above.

FIG. 1 b shows a basic design advantage of the invention. This advantageallows for the sub-micron or fine-lines, that run in the immediatevicinity of the metal layers 3 and the contact points 6, to be extendedin an upward direction 20 through metal interconnect 71 formed in theopenings 7 of the insulating polymer layer 5 and in the openings 7′ ofthe passivation layer 4. This extension continues in the direction 22 inthe horizontal plane of the thick, wide metal interconnect 10 and comesback down in the downward direction 24 through metal interconnect 72formed in the openings 7 of the insulating polymer layer 5 and in theopenings 7′ of the passivation layer 4. The functions and constructs ofthe passivation layer 4 and the insulating polymer layer 5 remain aspreviously highlighted. This basic design advantage of the invention isto “elevate” or “fan-up” the fine-line interconnects and to remove theseinterconnects from the micron and sub-micron level to a post-passivationmetal interconnect level that has considerably larger dimensions and istherefore characterized by smaller resistance and capacitance and iseasier and more cost effective to manufacture. It therefore further addsto the importance of the invention in that it makes micron andsub-micron wiring accessible at a wide-metal level. The interconnections71 and 72 interconnect the fine-level metal by going up through thepassivation and polymer or polyimide dielectric layers, traverses over adistance on the thick, wide-metal level and continues by descending fromthe thick, wide-metal level back down to the fine-metal level by againtraversing down through the passivation and polymer or polyimidedielectric layers. The extensions that are in this manner accomplishedneed not to be limited to extending fine-metal interconnect points 6 ofany particular type, such as signal or power or ground, with thick, widemetal line 26.

FIGS. 4 a and 4 b show how the interconnect aspect of the invention (asshown by arrows 20/22/24 of FIG. 1 b) can further be extended to addexternal power, ground and signal distribution. This allows two portionsof an internal circuit to be connected externally using a single pin-inor pin-out. Top polymer layer 16 has an opening 28 for the externalconnection. Connections to the next level of packaging may be madethrough solder bumps, gold bumps, or wirebonds. There is the possibilityof many contact points to the next level package. In this case, the nextlevel package, for example, a BGA substrate, requires fine pitch metalsto accommodate these many contact points. By being able to readilyextend the post-passivation metal dimensions it also becomes possible tointerconnect power, ground and signal lines at a post-passivation metallevel thereby reducing the cost and complexity of performing thisfunction in a BGA substrate. FIG. 4 b further shows opening 29 in thepassivation layer 4 made to a top layer 6 of the fine-lineinterconnection metallization structure. Opening 28 is made to an uppercontact point 26 in the thick, wide metallization structure whileopening 29 is made to a lower contact point 6 in the fine-lineinterconnection metallization structure. Connections to the next levelof packaging may be made to the lower contact point through opening 29through solder bumps, gold bumps, or wirebonds.

FIGS. 5 through 8 show further detail to demonstrate the concepts offan-out, pad relocation, the creation of common ground, power and signalpads, and the creation of additional pads.

FIG. 5 a shows the concept of fan-out for a flip-chip on a BGAsubstrate. A cross section of an integrated circuit 100 is shown withfive solder bumps 101 through 105. By using a BGA substrate 130 and thewiring 107 within the substrate 130, bump 101 can be repositioned tolocation 111, bump 102 to location 112, etc. for the remaining solderbumps 103 through 105. The separation of contact points 111 through 115is considerably larger than the separation of the original solder bumps101 through 105. The BGA substrate allows for spreading the distancebetween the contact points or bumps of the BGA device.

FIG. 6 a shows the concept of pad relocation for a flip chip on a BGAsubstrate. Contact bumps 101 through 105 are shown. By using BGAsubstrate 130 and the wiring 131 that is provided within the substrate,the BGA pads can be arranged in a different and arbitrary sequence thatis required for further circuit design or packaging. For instancecontact bump 101, which is on the far left side of the IC 100, isre-routed to location 124 which is on the second far right of the BGAsubstrate 130. The re-arrangements of the other BGA solder bumps canreadily be learned from following the wiring 131 within the substrate130 and by tracing from solder bump to one of the contact points 121through 125 of the BGA substrate.

FIG. 7 a shows pad reduction, the interconnecting of solder bumps intocommon power, ground or signal pads on a flip-chip BGA substrate. The IC100 is again shown with five solder bumps 101 through 105. The BGAsubstrate 130 contains a wiring scheme that contains in this examplethree wiring units, one for each for the power, ground and signal bumpsof the IC. Wire arrangement 132 connects solder bumps 101, 103 and 105to interconnect point 138 of the BGA substrate 130. It can further beseen that solder bump 104 is connected to interconnect point 140 of theBGA substrate by means of the wire arrangement 136, while solder bump102 is connected to interconnect point 142 of the BGA substrate by meansof the wire arrangement 134. The number of pins required to interconnectthe IC 100 is in this manner reduced from five to three. For more solderbumps, as is the case for a typical flip-chip IC, the numeric effect ofthe indicated wiring arrangement is considerably more beneficial.

FIG. 8 a shows pad addition, the interconnecting of single solder bumpsinto several contact points on a flip-chip BGA substrate. The IC 100 isshown with three solder bumps 101, 103, 105. The BGA substrate 130contains a wiring scheme that contains in this example three wiringunits. Wire arrangement 153 connects solder bump 103 to threeinterconnect points 161, 163 and 165 of the BGA substrate 130. It canfurther be seen that solder bump 101 is connected to interconnect point162 of the BGA substrate by means of the wire arrangement 151, whilesolder bump 105 is connected to interconnect point 164 of the BGAsubstrate by means of the wire arrangement 155. The number of pinsrequired to interconnect the IC 100 is in this manner increased fromthree to five. The added two contact points 161, 165 on the BGAsubstrate are useful for connecting to the next level package.

The concept of fan-out, pad relocation, pad reduction, and pad additioncan be realized using the post-passivation metal interconnection schemedescribed in this invention, to replace the function of BGA substrate130. From FIGS. 5 b, 6 b, 7 b, and 8 b, it can be seen that the extendedfunctionality and extended wiring ability that are provided by theinterconnect wiring schemes that are typically created in the BGAsubstrate 130 can be created using the method of the invention, ondevice 100. Some of the methods and possibilities of interconnect linerouting that can be implemented using the method of the invention arehighlighted in the following paragraphs.

Fan-out capability can be provided by the invention, using the metalconductors within the openings through the passivation layer thatconnect electrical contact pads of the top metallization structure withcontact points of the interconnecting metallization structure. FIG. 5 bshows a schematic view of the connections between the post-passivationmetal pads 111-115 and the fine line metal pads 101-105 using fan-out.Each of the electrical contact points of the interconnectingmetallization structure is connected directly and sequentially with atleast one electrical contact point of the post-passivation metallizationstructure. In a fan-out scheme, the distance between electrical contactpoints of the post-passivation metallization structure is larger thanthe distance between electrical contact points of the fine lineinterconnecting metallization structure.

Pad relocation may also be accomplished by the method of the invention.FIG. 6 b is a schematic view of connections between post-passivationmetal pads 121-125 and fine line metal pads 101-105, showing padrelocation. Electrical contact points of the post-passivationmetallization structure are connected with the contact points of thefine line interconnecting metallization structure, directly but notnecessarily sequentially, thereby creating a pad relocation effect.

A reduction effect may also be accomplished by the method of theinvention, wherein common nodes are connected together. FIG. 7 b shows aschematic view of connections between post-passivation metal pads 138,140, and 142 and fine line metal pads 101-105. Electrical contact pointsof the post-passivation metallization structure are connected withcontact points of the fine line interconnecting metallization structure,where fewer contact points are used in the post-passivationmetallization structure, since functionally equivalent contact points inthe fine line interconnecting metallization structure are connectedtogether. That is, the number of contact points for a particularelectrical function among the electrical contact points of thepost-passivation metallization structure is smaller than the number ofelectrical contact points of the fine line interconnecting metallizationstructure.

An addition effect may also be accomplished by the method of theinvention, wherein a single node is connected to several contact pointsat different locations. FIG. 8 b shows a schematic view of connectionsbetween post-passivation metal pads 161-165 and fine line metal pads101, 103 and 105. Electrical contact points of the post-passivationmetallization structure are connected with contact points of the fineline interconnecting metallization structure, where more contact pointsare used in the post-passivation metallization structure, since a singlepoint in the fine line interconnecting metallization structure isconnected to several contacts on the post-passivation metal structurewith equivalent electrical functionality. That is, the number of contactpoints for a particular electrical function among the electrical contactpoints of the post-passivation metallization structure is greater thanthe number of electrical contact points of the fine line interconnectingmetallization structure.

Some of the advantages of the present invention are:

1) improved speed of the IC interconnections due to the use of thick,wide metal lines (which results in lower resistance) and thickerdielectrics between the interconnecting lines (which results in lowercapacitance and reduced RC delay). The improved speed of the ICinterconnections results in improved performance of High PerformanceIC's.2) an inexpensive manufacturing process since there is no need forexpensive equipment that is typically used in sub-micron IC fabrication;there is also no need for the extreme clean room facilities (class 10 orless) that are typically required for sub-micron manufacturing. Class100 or more clean rooms can be used for the post-passivation process ofthe invention.3) power/ground buses and clock distribution networks are easier tointegrate within the design of IC's.4) system-on-chip designs will benefit from the present invention sinceit allows ready and cost effective interconnection between functionalcircuits that are positioned at relatively large distances from eachother on the chip.5) form the basis for a computer based routing tool that automaticallyroutes interconnections that exceed a pre-determined length inaccordance with the type of interconnection that needs to beestablished.6) provide a means to standardize BGA packaging. That is, acustomization usually achieved by wiring in the BGA substrate can bemoved to the post-passivation metallization structure of the invention.7) be applicable to solder bumps, gold bumps, and wirebonding for makingfurther circuit interconnects.8) provide a means for fan-out, relocation, and pad number reduction andaddition using solder bump, wirebond, and gold bump.9) provide a means for pad fan-out, relocation, reduction and additionthereby providing increased flexibility. By fan-out, relocation,reduction and addition of the pads, flexibility for fitting intovarieties of next level packaging by wirebonding, solder bumps or goldbumps is achieved. This flexibility in pad location, pad number and padarrangement is very useful in system-in-package and multi-chip moduleapproaches.10) provide a means for common power, ground and signal lines therebyreducing the number of pins required to interconnect with surroundingcircuits.11) provide a means for fan-up function by the application of smallpassivation (0.1 micrometers or more) vias.12) provide the means for extending a fine-wire interconnect scheme to awide-wire interconnect scheme.13) replace BGA interconnections by providing finer-than-BGA-substratemetal design rules on the post-passivation metal scheme. The BGA designcan therefore be simplified, and the cost is greatly reduced.

Although the preferred embodiment of the present invention has beenillustrated, and that form has been described in detail, it will bereadily understood by those skilled in the art that variousmodifications may be made therein without departing from the spirit ofthe invention or from the scope of the appended claims.

1. A chip comprising: a silicon substrate; a first dielectric layer oversaid silicon substrate; a transistor under said first dielectric layer;a metallization structure over said first dielectric layer, wherein saidmetallization structure comprises a first metal layer and a second metallayer over said first metal layer; a second dielectric layer betweensaid first and second metal layers; a passivation layer over saidmetallization structure and over said first and second dielectriclayers, wherein said passivation layer comprises a nitride layer; afirst polymer layer on said passivation layer, wherein a first openingin said first polymer layer is over a first contact point of saidmetallization structure and exposes said first contact point; a thirdmetal layer on said first polymer layer, on said first contact point andin said first opening, wherein a first dip at a top of said third metallayer is over said first contact point; a second polymer layer on saidthird metal layer and on said first polymer layer, wherein said secondpolymer layer has a top polished surface, and wherein over said firstdip is no dip at a top of said second polymer layer; and a fourth metallayer on said top polished surface and over said first dip.
 2. The chipof claim 1, wherein a second opening in said first polymer layer is overa second contact point of said metallization structure and exposes saidsecond contact point, wherein said third metal layer is further on saidsecond contact point, wherein said first contact point is connected tosaid second contact point through said third metal layer, wherein asecond dip at said top of said third metal layer is over said secondcontact point, and wherein over said second dip is no dip at said top ofsaid second polymer layer.
 3. The chip of claim 1, wherein said thirdmetal layer comprises a copper layer having a thickness between 2 and100 micrometers.
 4. The chip of claim 1, wherein said fourth metal layercomprises a titanium-containing layer and a copper layer over saidtitanium-containing layer.
 5. The chip of claim 1, wherein said thirdmetal layer comprises a gold layer having a thickness between 2 and 100micrometers.
 6. The chip of claim 1, wherein said fourth metal layercomprises a titanium-containing layer and a gold layer over saidtitanium-containing layer.
 7. The chip of claim 1, wherein said firstpolymer layer comprises polyimide.
 8. The chip of claim 1, wherein saidfirst polymer layer has a thickness between 2 and 100 micrometers. 9.The chip of claim 1, wherein said nitride layer has a thickness greaterthan 0.3 micrometers.
 10. A chip comprising: a silicon substrate; afirst dielectric layer over said silicon substrate; a transistor undersaid first dielectric layer; a metallization structure over said firstdielectric layer, wherein said metallization structure comprises a firstmetal layer and a second metal layer over said first metal layer; asecond dielectric layer between said first and second metal layers; apassivation layer over said metallization structure and over said firstand second dielectric layers, wherein said passivation layer comprises anitride layer; a third metal layer over said passivation layer, whereina gap is between two portions of said third metal layer; a first polymerlayer on said third metal layer and in said gap, wherein said firstpolymer layer has a top polished surface, and wherein over said gap isno dip at a top of said first polymer layer; and a fourth metal layer onsaid top polished surface and over said gap.
 11. The chip of claim 10further comprising a second polymer layer between said third metal layerand said passivation layer.
 12. The chip of claim 10, wherein said thirdmetal layer comprises a titanium-containing layer and a copper layerover said titanium-containing layer.
 13. The chip of claim 10, whereinsaid fourth metal layer comprises a copper layer having a thicknessbetween 2 and 100 micrometers.
 14. The chip of claim 10, wherein saidthird metal layer comprises a titanium-containing layer and a gold layerover said titanium-containing layer.
 15. The chip of claim 10, whereinsaid fourth metal layer comprises a gold layer having a thicknessbetween 2 and 100 micrometers.
 16. The chip of claim 10, wherein saidfirst polymer layer comprises polyimide.
 17. The chip of claim 10,wherein said nitride layer has a thickness greater than 0.3 micrometers.18. A chip comprising: a silicon substrate; a first dielectric layerover said silicon substrate; a transistor under said first dielectriclayer; a metallization structure over said first dielectric layer,wherein said first metallization structure comprises a first metallayer, a second metal layer over said first metal layer, and a thirdmetal layer over said second metal layer; a second dielectric layerbetween said first and second metal layers; a first insulating layerbetween said second and third metal layers; a second insulating layerover said metallization layer, over said first and second dielectriclayers and over said first insulating layer, wherein an opening in saidsecond insulating layer is over a contact point of said metallizationstructure and exposes said contact point, and wherein said secondinsulating layer has a top polished surface; and a fourth metal layer onsaid top polished surface and on said contact point, wherein said fourthmetal layer is connected to said contact point through said opening, andwherein said fourth metal layer comprises a titanium-containing layerand a gold layer having a thickness between 2 and 100 micrometers oversaid titanium-containing layer.
 19. The chip of claim 18, wherein saidsecond insulating layer comprises polyimide.
 20. The chip of claim 18,wherein said titanium-containing layer comprises a titanium-tungstenalloy.